In recent years, the sizes of electronic devices have been progressively downsized, and concomitant therewith, the downsizing in size of positive temperature coefficient thermistors mounted in the above-mentioned electronic devices has also been implemented. The positive temperature coefficient thermistor described above has a positive resistance temperature characteristic, and as a downsized positive temperature coefficient thermistor, for example, a multilayer positive temperature coefficient thermistor is known.
This type multilayer positive temperature coefficient thermistor described above generally has a ceramic body which includes a plurality of semiconductor ceramic layers each having a positive resistance temperature characteristic and a plurality of internal electrode layers formed along interfaces between the semiconductor ceramic layers, the internal electrode layers are alternately extended to two end portions of the ceramic body, and external electrodes are also formed so as to be electrically connected to the internal electrode layers thus extended. In addition, as the semiconductor ceramic layer, a material primarily containing a BaTiO3-based ceramic material is used. Furthermore, in order to obtain a positive resistance temperature characteristic by a BaTiO3-based ceramic material, an extremely small amount of a semiconductor dopant is added thereto, and as this semiconductor dopant, in general, samarium (Sm) has been widely used.
In addition, as an internal electrode material used in the multilayer positive temperature coefficient thermistor, Ni has been widely used. In general, the ceramic body of the multilayer positive temperature coefficient thermistor is formed by the steps of performing screen printing of an internal electrode conductive paste on ceramic green sheets to be formed into the semiconductor ceramic layers to form conductive patterns, laminating the ceramic green sheets provided with the conductive patterns in a predetermined order, and simultaneously firing the ceramic green sheets and the conductive patterns.
Moreover, when Ni is used as the internal electrode material, the simultaneous firing must be performed in a reducing atmosphere since Ni is oxidized when simultaneous firing is performed in an air atmosphere. However, when the simultaneous firing is performed in a reducing atmosphere, the semiconductor ceramic layers are also reduced. As a result, a sufficient rate of resistance change cannot be obtained. Accordingly, in general, after the simultaneous firing is performed in a reducing atmosphere, a re-oxidation treatment is additionally performed in an air atmosphere or in an oxygen atmosphere.
However, in this re-oxidation treatment, a heat treatment temperature is difficult to control, and it is not easy to diffuse oxygen sufficiently to a central portion of the ceramic body; hence, oxidation is irregularly performed thereby, and as a result, a sufficient rate of resistance change may not be obtained in some cases.
Accordingly, in Patent Document 1, a multilayer positive temperature coefficient thermistor has been proposed in which a void ratio of semiconductor ceramic layers is set in the range of 5 to 40 percent by volume, and among thermistor layers, which are effective layers provided between two internal electrodes located at the outermost sides in the lamination direction, the void ratio of a thermistor layer located at a central portion in the lamination direction is higher than that of a thermistor layer located outside in the lamination direction.
According to the Patent Document 1, although the void ratio of the semiconductor ceramic layers are set in the range of 5 to 40 percent by volume, when this void ratio is converted into a sintered density, the sintered density thus converted approximately corresponds to 60% to 95% of a theoretical sintered density. In addition, according to this Patent Document 1, an actual-measured sintered density of the semiconductor ceramic layers is decreased to 60% to 95% of the theoretical sintered density, and the void ratio of the thermistor layer located at the central portion is increased larger than that of the thermistor layer located outside, so that oxygen can be easily diffused sufficiently to the central portion of the ceramic body; hence, as a result, by preventing the generation of irregular oxidation, it is intended to obtain a desired rate of resistance change.
On the other hand, after ceramic green sheets to be formed into the semiconductor ceramic layers and conductive patterns to be formed into the internal electrode layers are simultaneously fired in a reducing atmosphere, heat treating is performed in an air atmosphere or an oxygen atmosphere. Since many thermal and atmospheric histories are applied to the semiconductor ceramic layers, strains are generated therein. As a result, the rate of temporal change in room-temperature resistance may be increased in some cases.
Accordingly, as a method for decreasing the rate of temporal change in room-temperature resistance described above, as disclosed in Patent Document 2, a method for manufacturing a multilayer positive temperature coefficient thermistor has been proposed in which a heat treatment is performed on a ceramic body provided with external electrodes at a temperature of 60 to 200° C.
In this Patent Document 2, by performing the heat treatment at a temperature of 60 to 200° C. after the external electrodes are formed on the ceramic body, it is attempted to gradually reduce the strains generated in the semiconductor ceramic layers and to stabilize the rate of temporal change in room-temperature resistance.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-93574
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2004-134744
According to the manufacturing method disclosed in the Patent Document 2, the heat treatment is performed at a temperature of 60 to 200° C. However, in order to stabilize the rate of temporal change in room-temperature resistance, it is believed that a heat treatment for approximately 100 hours be required (see paragraph [0023] of the Patent Document 2). Hence, the heat treatment takes a long period of time, and the production efficiency is degraded, and a problem of inferior mass productivity may be caused.
In addition, as disclosed in the Patent Document 1, in the case in which Sm is used as the semiconductor dopant, when the sintered density of the semiconductor ceramic layer is low, the inter-particle bond thereof is also weak, and the crystal lattice becomes unstable; hence, even when the heat treatment is performed as disclosed in the Patent Document 2, it is difficult to sufficiently stabilize the rate of temporal change in room-temperature resistance.